The present invention concerns an antisaturation circuit for PNP transistors in monolithic integrated circuits. Such integrated circuits are formed on a single chip of semiconductor material, usually silicon, by a suitable sequence of fabrication stages comprising superficial oxidation, photolithography, epitaxial growth, diffusion of impurities, and metallizations. With these processes, diodes, transistors and passive components are formed and are interconnected on the chip itself by means of successive metallization and isolation layers.
Integrated PNP transistors formed on the semiconductor chip present, during their operation, a peculiar problem. Under certain conditions, when the PNP transistor is working in the saturation zone of its characteristic, it may give rise to a leakage current toward the substrate which may be intolerable for the correct operation of the whole integrated circuit. In saturation conditions, which occur with the substantial dropping to zero of the V.sub.CE voltage of the PNP transistor, its base may, for example, come to find itself at a lower potential than the potential of its collector making it possible for the base-collector junction to become forward biased. This gives rise to the creation of a "parasitic PNP transistor" through the base-collector junction of the real transistor, whose collector functions as the "emitter" of the "parasitic transistor", the "collector" is represented by the substrate of semiconductor material of the chip.
Naturally, this problem is particularly felt in the case of integrated PNP power transistors because of the magnitude of the currents, as well as the increased probability that such transistors might be driven accidentally into their zone of saturation with the variation of the load impedance of the transistor.
In Italian patent application No. 21272 A/85, filed on June 24, 1985, by the present applicant, SGS-MICROELETTRONI CA S.p.A., a simple and effective antisaturation circuit was proposed in order to limit the degree of saturation of an integrated PNP transistor and therefore of the leakage current toward the substrate.
Nevertheless, such a circuit does not lend itself to predisposing a specific characteristic of intervention, as is often desirable in certain applications of PNP power transistors.